Decoders & Plexers
CircuitVerse features the following circuit elements in this category:
- Multiplexer
- Demultiplexer
- BitSelector
- Most Significant Bit (MSB) Detector
- Least Significant Bit (LSB) Detector
- Priority Encoder
- Decoder
- Parity Generator & Parity Detector
Multiplexer
A Multiplexer selectively passes only one of the inputs provided to it using a control signal. The number of inputs is always a power of 2. If there are N control bits, then there can be a maximum of 2^N inputs.
Properties that can be customized in the PROPERTIES panel include: BitWidth, Control Signal Size
Consider a 2 to 1 multiplexer that takes two single-bit inputs (T1 and T2), a single-bit control signal (S) and has an output (Out). Using Table 4.1, you can verify the behavior of a 2 to 1 multiplexer.
Table 4.1: Truth table of a 2 to 1 multiplexer
| S | Out |
| 0 | T1 |
| 1 | T2 |
Using Table 4.2, you can verify the behavior of the Multiplexer circuit element in the live circuit of a 4 to 1 multiplexer embedded below:
Table 4.2: Truth table of a 4 to 1 multiplexer
| S1 | S0 | Out |
| 0 | 0 | T1 |
| 0 | 1 | T2 |
| 1 | 0 | T3 |
| 1 | 1 | T4 |
Demultiplexer
A Demultiplexer takes an input and passes it to only one of outputs using a control signal. The number of outputs is always a power of 2. If there are N control bits, we can choose to pass the output to any one of the 2^N output lines.
Properties that can be customized in the PROPERTIES panel include: BitWidth, Control Signal Size
In the live circuit embedded below, a 1 to 2 demultiplexer takes in a single-bit input (T), a single-bit control signal (S) and two single-bit outputs (O1 and O2). Table 4.3 displays the truth table of a 1 to 2 demultiplexer.
Table 4.3: Truth table of a 1 to 2 demultiplexer
| S | O1 | O2 |
| 0 | T | 0 |
| 1 | 0 | T |
In another example of a live circuit embedded below, a 1 to 4 demultiplexer takes in a three-bit input and a two-bit control signal. Table 4.4 displays the truth table of a 1 to 4 demultiplexer.
Table 4.4: Truth table of a 1 to 4 demultiplexer
| S1 | S0 | O1 | O2 | O3 | O4 |
| 0 | 0 | T | 0 | 0 | 0 |
| 0 | 1 | 0 | T | 0 | 0 |
| 1 | 0 | 0 | 0 | T | 0 |
| 1 | 1 | 0 | 0 | 0 | T |
BitSelector
As its name suggests, the BitSelector circuit element takes a single or multi-bit input and outputs the bit that must be isolated using a single or multi-bit select line. The select line value indicates the specific bit that must be isolated within its body in decimal form.
Properties that can be customized in the PROPERTIES panel include: BitWidth, Selector Bit Width
In the live circuit embedded below, a BitSelector with a four-bit input is used. Each of its bits can be addressed separately as T3, T2, T1, T0 (from most significant to least significant). It also includes a two-bit select line (S1 and S0) and a single-bit output (Out). Table 4.5 displays the truth table of a four-bit BitSelector.
Table 4.5: Truth table of a four-bit bit selector
| S1 | S0 | Out |
| 0 | 0 | T0 |
| 0 | 1 | T1 |
| 1 | 0 | T2 |
| 1 | 1 | T3 |
Most Significant Bit (MSB) Detector
The Most Significant Bit (MSB) detector circuit element outputs the bit position of the most significant bit of the input. In other words, it outputs the bit position of the rightmost bit. An enable output is also provided to show if the MSB detector is active. The bit position of the MSB is also shown in decimal form within the body of the MSB detector.
You can verify the behavior of the Most Significant Bit (MSB) detector circuit element with a four-bit input in the live circuit embedded below:
Least Significant Bit (LSB) Detector
The Least Significant Bit (LSB) detector circuit element outputs the bit position of the least significant bit of the input. In other words, it outputs the bit position of the leftmost bit. An enable output is also provided to show if the LSB detector is active. The bit position of the LSB is also shown in decimal form within the body of the LSB detector.
You can verify the behavior of the Least Significant Bit (LSB) detector circuit element with a four-bit input in the live circuit embedded below:
Priority Encoder
The Priority Encoder circuit element works similarly to the MSB and LSB detectors. There is a specific output based on the bit position of the MSB, irrespective of the lesser significant bits. An enable input is also provided to activate/deactivate the priority encoder. If there are N outputs, there will be 2^N inputs.
In the live circuit embedded below, a Priority Encoder with four single-bit inputs (T3, T2, T1, and T0 from most to least-significant bit) and two single-bit outputs (O2 and O1 from most to least-significant bit). Table 4.6 displays the truth table of the four-input priority encoder.
Properties that can be customized in the PROPERTIES panel include: BitWidth
Table 4.6: Truth table of a four-input priority encoder
| T3 | T2 | T1 | T0 | O2 | O1 |
| 0 | 0 | 0 | 1 | 0 | 0 |
| 0 | 0 | 1 | X | 0 | 1 |
| 0 | 1 | X | X | 1 | 0 |
| 1 | X | X | X | 1 | 1 |
Decoder
The Decoder circuit element includes N input bits and has 2^N output lines.
In the live circuit embedded below, a Decoder with a single two-bit input (T1 and T0 from most to least-significant bit) and four single-bit output lines (O4, O3, O2, and O1 from most to least-significant bit). For the input values set in T1 and T0, the corresponding output line (O4, O3, O2, and O1) is HIGH. Table 4.7 displays the truth table for a two-bit decoder.
Properties that can be customized in the PROPERTIES panel include: BitWidth
Table 4.7: Truth table of a two-bit decoder
| T1 | T0 | O4 | O3 | O2 | O1 |
| 0 | 0 | 0 | 0 | 0 | 1 |
| 0 | 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 0 | 1 | 0 | 0 |
| 1 | 1 | 1 | 0 | 0 | 0 |
Parity Generator & Parity Detector
The Parity Generator and Parity Detector combinational circuit elements are used together for error-tolerant data transmission. The Parity Generator circuit element is used by the sender, and the Parity Detector circuit element is used by the receiver.
Parity Generator
The Parity Generator circuit element generates a parity bit which is later used by parity detectors to detect errors in data transmission. The parity bit is added to the original message that must be sent.
If the input message of an even parity generator has an even number of 1s, the parity bit will be 0. On the other hand, if there are an odd number of 1s, the parity bit generated will be 1. Table 4.8 displays the truth table for an even three-bit input parity generator.
Table 4.8: Truth table for an even three-bit parity generator
| A | B | C | PARITY BIT (P) |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 |
If the input message of an odd parity generator has an even number of 1s, the parity bit will be 1. Alternatively, if there are an odd number of 1s, the parity bit generated will be 0. The parity bit generated is then added to the message to be sent. Table 4.9 displays the truth table for an odd three-bit input parity generator.
Table 4.9: Truth table for an odd three-bit parity generator
| A | B | C | PARITY BIT (P) |
| 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 |
Parity Detector
The Parity Detector circuit element receives the message and checks it for errors. If an error is detected, the parity error check bit gives 1 as output and 0 when no error is detected. Table 4.10 and Table 4.11 display the truth tables for an even and odd three-bit input parity detector, respectively.
| A | B | C | P | PARITY ERROR CHECK |
| 0 | 0 | 0 | 1 | 1 |
| 0 | 0 | 1 | 0 | 1 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 0 | 1 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 |
| 1 | 0 | 1 | 1 | 1 |
| 1 | 1 | 0 | 0 | 0 |
| 1 | 1 | 0 | 1 | 1 |
| 1 | 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 | 0 |
| A | B | C | P | PARITY ERROR CHECK |
| 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 |
| 0 | 0 | 1 | 1 | 1 |
| 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 1 |
| 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 1 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 | 1 |
Although the parity detector can detect most errors, some of its limitations include:
- Error is detected only if there are an odd number of error bits.
- Error in parity bit might lead to error detection despite correct transmission.
- Parity detector will not be able to detect errors where both parity and data bits have such an error that matches the parity bit.
You can verify the same in the live circuit embedded below: